Recently, malfunction of memory cell by incidence of .alpha. particles has been becoming a problem, with high integration of semiconductor memory devices. In order to solve this problem, Error Check and Correction (ECC) functions are provided on the same substrate of the semiconductor memory devices. In other words, on-chip ECC is provided. Such ECC functions are disclosed in, for example, an article by C. L. Chen and M. Y. Hsiao, entitled "Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review", IMB J. Res. Develop, vol. 28, No. 2 (1984), pp. 124-134; Japanese Laying-Open Gazette No. 143600/1981 entitled "Device for Preventing Errors from Cumulating in Data; and an article by M. D. Quinn and D. Richter, entitled "Dynamic Testing of Memory Arrays which Utilize ECC Logic", Electronic Engineering, March, 1981, pp. 111-119.
FIG. 1 is a schematic block diagram showing an example of a conventional on-chip ECC circuit using Hamming codes for error correction.
First, structure of the conventional on-chip ECC circuit shown in FIG. 1 will be described. In FIG. 1, a plurality of data bits a (m bits) are applied to an input terminal 1. The data bits a are applied to both a data bit memory cell array 3 and a write check bit generating circuit 2. The write check bit generating circuit 2 generates write check bits b including k bits from the data bits a including m bits, and applies them to a check bit memory cell array 4. The data bit memory cell array 3 and the check bit memory cell array 4 constitute a memory cell array 5. In addition, the data bit memory cell array 3 outputs new data bits c including m bits, and applies them to both a read check bit generating circuit 6 and a data correction circuit 9. The check bit memory cell array 4 outputs new write check bits d including k bits, and applies them to both a syndrome generating circuit 7 and the data correction circuit 9. The read check bit generating circuit 6 generates new read check bits e including k bits from the data bits c including m bits, and applies them to the syndrome generating circuit 7. The syndrome generating circuit 7 performs an Exclusive-OR operation of the read check bits e and the write check bits d, so that a syndrome f including k bits is applied to a syndrome decoder 8. The syndrome decoder 8 decodes the syndrome f, so that syndrome decoding data g including (m+k) bits is applied to the data correction circuit 9. The data correction circuit 9 corrects the data bits c and the write check bits d responsive to the syndrome decoding data g, so that the corrected data h is applied to the memory cell array 5 and an external output data i is applied to an address decoder 10. The address decoder 10 selects the external output data j according to address information l, which data j is outputted through an output terminal 11.
Now, an operation of the conventional on-chip ECC circuit shown in FIG. 1 will be described.
First, the data bit a inputted into the input terminal 1 is written into the data bit memory cell array 3 and at the same time, is applied to the write check bit generating circuit 2. The write check bit generating circuit 2 is a circuit generating check bits including k bits from data bits including m bits. The read check bit generating circuit 6 has the same construction and functions as those of the circuit 2. The check bits b, including k bits generated from the data bits a in the write check bit generating circuit 2, is written into the check bit memory cell array 4. A block of (m+k) bits (referred to as a "ECC code word" hereinafter) comprising the data bits a, including m bits and the check bits b, including k bits becomes a unit of bit for ECC, and the error check and correction is performed for each ECC code word.
Then, when data is read out fromthe memory cell array 5, the data bits c including m bits and the check bits d including k bits are concurrently read out from the data bit memory cell array 3 and the check bit memory cell array 4, respectively. The read check bit generating circuit 6 generates the read check bits e including k bits from the data bits c including m bits, and applies them to the syndrome generating circuit 7. The syndrome generating circuit 7 is a circuit performing an Exclusive OR operation for each bit of the read check bits e, including k bits and the write check bits d, including the same k bits. As a result of this operation, the read check bits e coincide with the write check bits d, if the result of Exclusive OR operation by the syndrome generating circuit 7 is logical "0"; that is, all bits of the syndrome f which is a data train of k bits are lotical "0". In other words, In other words, "there is no error" in such a case. Conversely "there is an error" in the other case. Since the syndrome f of the data train of k bits as described above includes information concerning location of error bit, it can be identified by decoding the syndrome f, which bit out of data bits including m bits is erroneous.
More particularly, the syndrome detector 8 is a decoder converting the syndrome f of k bits into a code of (m+k) bits designating error bit out of the data bits including m bits and the check bits including k bits. For example, output having logical "1"s only at error bit locations out of (m+k) bits and logical "0"s at other bit locations. In addition, the data correction circuit 9 corrects or inverts the error bit or bits out of the above described (m+k) bits. That is, the data correction circuit 9 performs an Exclusive OR operation, for each bit, of the output g of the syndrome decoder 8 and the data bits c and the check bits d to be corrected, so that data only for the error bit or bits are inverted. The error corrected code of (m+k) bits is again written into a predetermined location in the memory cell array 5. Further, of the corrected data i of m bits, a corrected data of m.sub.0 (m.sub.0 &lt;m) bits is selected by the address decoder 10 in accordance with input address information l and is outputted as the external data output j. In most cases, a large part of the address decoder 10 can be used as an accessing decoder for the data bit memory cell array 3.
FIG. 2 is a circuit diagram showing the structure of the address decoder 10 in detail.
Referring to FIG. 2, the address decoder 10 basically comprises a switching circuit 12 and a main amplifier 13. Although the address decoder 10 receives the corrected data of (m+k) bits from the data correction circuit 9, only the data of m bits out of the corrected data of (m+k) bits is received by the switching circuit 12 in the address decoder 10. More specifically, word lines for only m bits from the data correction circuit 9 are connected to respective one conduction terminals of transistors 16-1 to 16-m constituting the switching circuit 12. The other conduction terminals of these transistors 16-1 to 16-m are connected to an input of the main amplifier 13. The main amplifier 13 amplifies the data inputted through a group of the transistors from the data correction circuit 9 and outputs the amplified data as data j. In addition, decoding signals d to d are applied to the control terminals of the transistors 16-l to 16-m, respectively. These decoding signals d.sub.1 to d.sub.m correspond to the input address information l as shown in FIG. 1. In the address decoder 10, the data of m.sub.0 bits out of the corrected data of m bits is selected in accordance with the input address information .phi., (decoding signals d.sub.l to d.sub.m), and outputted as the external data output j.
The address decoder 10 comprises conventional means for writing data of (m+k) bits into the memory cell array 5. However, for simplification of illustration, such conventional portion is omitted from FIG. 2.
It can be appreciated, however, that ECC performed according to the semiconductor memory device as structured and described above, external testing of functionality of check bit memory cell array 4 is impossible, since the check bit memory cell array 4 is not externally accessable to test, although the data bit memory cell array 3 can be externally accessed and tested through the switching circuit 12 in the addressing decoder 10.
In an dynamic type of semiconductor memory device comprising an on-chip ECC function, it is generally desirable to have all of the data bits and check bits included in the same ECC code word placed on the same word line. This placement would allow all of data bits and check bits to be internally and concurrently read out, and the ECC system to be easily constructed.
On the other hand, in order to independently and externally test a data bit memory cell array and check bit memory cell array using external testing means, external direct accexss, in other words, read/write functions must be enabled for not only the data bit memory cell array but also the check bit memory cell array. Generally, in order to make such external direct access possible, it is necessary to disconnect and/or disable the conventional ECC circuit system including the circuits 2, 6, 7, 8 and 9 when testing, and alternately to (a) test the check bit memory cell array; and (b) test the data bit memory cell array, by means of an external testing means.
However, the test mode control system necessary would be complicated and costly, since at least two kinds of switching means for the above described testings (a) and (b) would be required.